Freescale Semiconductor /MK70F12 /DDR /CR04

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR04

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBINT0TRRD0TRC0TRASMIN

Description

DDR Control Register 4

Fields

TBINT

Time Burst Interrupt Interval

TRRD

Defines the DRAM activate-to-activate delay for different banks (TRRD) in cycles.

TRC

Defines the DRAM period between active commands for the same bank (TRC) in cycles.

TRASMIN

Time RAS Minimum

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